(image: KobizMedia/ Korea Bizwire)
SANTA CLARA, Calif., Jun. 11 (Korea Bizwire) — MIPS, provider of the widely used MIPS processor architecture and IP cores for licensing, today announced that its I6500-F CPU IP core, designed as a Safety Element out of Context (SEooC), is the first high performance 64 bit multi-cluster CPU IP to receive formal certification of compliance for ASIL B [D], based on ISO 26262: 1st edition 2011 (&DIS 2nd Edition 2018) and IEC 61508 SIL 2. The core was certified by Resiltech, a leader in certification of safety-related products for automotive and industrial applications.
“The I6500-F has been successfully assessed to be compliant to the latest ISO 26262 [including DIS ISO 26262, 2nd edition] and IEC 61508 safety standard and the MIPS team has followed the safety requirements, not only to address quantitative requirements for random failures for ASIL B [D], but also to achieve compliance regarding the systematic failure requirements. The safety compliance and the resulting safety cases will be of great value to the component vendors,” said Dr. Francesco Rossi, Automotive Safety Solutions Manager, Resiltech s.r.l
“Unlike ‘ASIL B/D ready’ solutions, the MIPS I6500-F has been developed as a SEooC, based on ASIL B [D] decomposition, for items targeting ASIL D automotive applications and delivers both safety and performance, an essential combination for extremely high system efficiency, scalable computing and compute-intensive tasks,” said David Lau, MIPS’ Vice President of Engineering. “The I6500-F is one of a new class of MIPS CPUs designed to ‘FortifAI’ next-generation intelligent applications. This ASIL B (D) SEooCs certification helps our customers significantly de-risk and accelerate certification at the SoC level.”
The MIPS I6500-F addresses the critical FuSa requirements for a wide range of automotive Human Machine Interface and ADAS/autonomous vehicle applications. These include speech and gesture recognition, eye tracking, driver monitoring, virtual assistance, and natural language interfaces, as well as camera-based machine vision, radar-based detection units, driver condition evaluation, and sensor fusion ECUs.
The MIPS I6500-F comes with a complete safety package, including all the required safety cases, quantitative safety analysis based on FMEDA, and safety analysis report summarizing the FMEDA analysis results and functional safety audit for addressing requirements for systematic failures.
“The I6500-F core from MIPS has helped us to reach new levels of performance, opening our platform and meeting our un-compromised functional safety goals,” said Elchanan Rushinek, Vice President, Engineering at Mobileye. “This certification underscores not only MIPS’ leading commitment to Functional Safety, but also to its partners and customers who rely on MIPS technology in highly intelligent and autonomous applications. We are continuing our collaboration with MIPS on FuSa compliance on our open platform.”
About MIPS
MIPS is a leading provider of processor architectures and IP cores that drive some of the world’s most popular products. With the streamlined MIPS RISC architecture and CPU cores, customers can build highly efficient, scalable, and trusted products across a wide range of performance points – from the IoT edge to high-end networking equipment, and everything in between. MIPS leads the industry with Multi-Threading capabilities for optimal application performance and efficiency. Originally founded in 1984 as MIPS Computer Systems Inc. by researchers from Stanford University, MIPS today is an independent company focused on processing innovations for a new generation of intelligent, connected devices. MIPS designs have shipped in billions of units across the globe and have even reached the outer edges of our solar system. The company is headquartered in Santa Clara, Calif., with offices worldwide. www.mips.com
MIPS and the MIPS logo are trademarks of MIPS in the United States and/or other countries. All other logos, products and trademarks are the property of their respective owners.
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Source: MIPS Tech via GLOBE NEWSWIRE
